做LLM集群硬件设计的朋友可以看看，这个框架能自动探索芯片间互连方案，在DeepSeek-R1上吞吐提升44%，内存省98%，还开源了。
C2C-Explorer是一个自适应贝叶斯设计空间探索框架，用于优化大语言模型云计算系统中的芯片间互连架构。该框架集成了LLM工作负载驱动的流量生成器、可扩展互连模拟器（支持交换机/全网格，最多512芯片）和指标引导评估器。模拟器经FPGA原型验证，端到端时序误差为2.46-8.23%，混合周期事件模型比纯周期精确基线加速7.8倍。在32-XPU DeepSeek-R1-671B推理工作负载上，C2C-Explorer将goodput提升44.1%，内存减少98.4%。该框架已开源。
C2C-Explorer: An Exploration Framework for Chip-to-Chip Interconnect Architectures in LLM Cloud Computing Systems
The scaling-up of large language models (LLMs) necessitates computing systems to have multi-processor-chip architectures, elevating the importance of chip-to-chip (C2C) communication. However, designing efficient C2C hardware architectures for LLM workloads faces three key challenges: generating realistic LLM-specific C2C traffic, accurately simulating hardware-level communication at scale, and efficiently exploring the exponentially large C2C design space. We propose C2C-Explorer, an adaptive Bayesian DSE framework that integrates a LLM-workload-driven traffic generator, a scalable interconnect simulator (switch/full-mesh, up to 512 chips), and a metric-guided evaluator into a workload-to-hardware optimization pipeline, enabling systematic C2C architectural co-design under realistic LLM workloads. Validated against FPGA-based C2C prototypes, the C2C simulator achieves 2.46-8.23% end-to-end timing error across diverse traffic patterns. Its hybrid cycle and event model further accelerates large-scale simulation by up to 7.8$\times$ over a pure cycle-accurate baseline. Applied to a 32-XPU DeepSeek-R1-671B inference workload, C2C-Explorer identifies configurations that improve goodput by 44.1% and reduce memory by 98.4%. C2C-Explorer is open-source and available at https://github.com/Selinaee/C2C-Explorer.