想用 LLM 做模拟电路设计的话，AaLLM 是开源端到端方案，给规格直接出网表，SPICE 调用和耗时都比现有方法少一个数量级。
AaLLM 是一个开源的端到端多智能体 LLM 工作流，输入规格即可输出网表，同时覆盖拓扑生成和电路尺寸确定。它从论文和教科书中自动构建知识库，并采用 RAG 模型模拟电路设计专家知识。AaLLM 使用设计师、评论家和评估器组成的三智能体反馈系统，减少尺寸迭代次数。生成的创新拓扑在品质因数上与已知拓扑相当，部分电路高出 3 倍。与最先进的多智能体 LLM 管线相比，SPICE 调用次数减少 3-4.5 倍，墙钟时间减少 40 倍。
AaLLM: An End-to-End Analog Circuit Design Framework from Topology Generation to Sizing Using Large Language Models
Analog circuit design is a time-consuming, iterative process in a nonlinear and high-dimensional design space that relies heavily on expert intuition. Among recent developments, LLMs have introduced a promising approach by bringing natural language reasoning to circuit design tasks. The majority of conventional LLM-based approaches provide fragmented solutions that focus either only on sizing or topology generation. These methods require adding specific technical knowledge manually, which is inefficient and prone to hallucinations during circuit sizing. Moreover, the inherent trade-off in meeting different specs makes current approaches iterative and tedious. Another shortcoming is the inability to create innovative topologies, which may lead to sub-optimal designs due to reliance on conventional topologies. In this paper, we present AaLLM, an open-source end-to-end multi-agent LLM workflow that takes user specs as input and outputs the appropriate netlist, encompassing both topology generation and circuit sizing. AaLLM automates the creation of a relevant knowledge base from research papers and textbooks to combat tedious manual data collection. A RAG model is implemented to emulate circuit design expertise using this knowledge base. Moreover, AaLLM uses a novel tri-agent feedback system comprising a Designer that determines circuit component values, a Critic that scrutinizes these values, and an Evaluator that minimizes circuit sizing iterations by arbitrating between the other two agents. AaLLM-generated novel topologies achieve a figure of merit (FoM) comparable to that of known topologies, and up to 3x higher for certain circuits. Testing on several circuit topologies, our results show a 3x - 4.5x decrease in the number of SPICE calls at inference when compared to SOTA multi-agent LLM pipelines. The results also show a 40x decrease in wall-clock time compared to existing approaches.