芯片设计从业者和关注半导体竞争格局的读者值得关注——LogicFolding 提出了从“缩小晶体管”到“减少时间浪费”的新范式，可能改变行业对性能提升的衡量标准。建议点开了解具体技术细节。
华为发布了一种名为 LogicFolding 的新型芯片设计方法，旨在通过减少信号传输延迟来提升性能，而非单纯追求晶体管尺寸缩小。该方法引入“τ scaling”概念，将芯片性能瓶颈从晶体管大小转向时间延迟的优化。LogicFolding 通过垂直堆叠有源电路层并用混合键合连接，缩短关键路径，降低延迟和能耗。这一突破有望帮助华为在芯片制造领域缩小与台积电的差距。
🇨🇳 Huawei just released breakthrough chip design a…
🇨🇳 Huawei just released breakthrough chip design approach "LogicFolding" that will close it's gap with TSMC.
The technical paper behind it.
The core idea is that chips should stop measuring progress mainly by how small transistors are and start measuring progress by how much time delay can be removed from the whole machine.
A chip wastes time when signals move through long wires, memory paths, chip-to-chip links, and software communication layers, so Huawei calls this delay τ, or tau.
Huawei’s paper introducing "LogicFolding" says the next chip breakthrough may come from cutting wasted time inside the machine.
That is what "τ scaling" means.
τ is the delay that accumulates before useful computing happens: a transistor switches, a signal crosses a wire, data reaches memory, a chip talks to another chip, or a server waits for a response.
Moore’s Law reduced this delay indirectly because shrinking transistors also shortened many of the paths around them.
But modern chips are no longer slowed only by transistor size.
They are slowed by wire resistance, parasitic capacitance, clock skew, memory distance, protocol conversion, chip-to-chip communication, and the cost of moving data.
So τ scaling changes the question from “how small is the transistor?” to “where is time being lost?”
LogicFolding is Huawei’s physical answer to that question inside a chip.
In a normal chip, related logic gates are spread across a flat surface, so signals often travel sideways through long metal routes before reaching the next important gate.
Those wires behave like sticky pipes: resistance slows current, capacitance must be charged and discharged, and every extra distance creates delay and wastes energy.
LogicFolding tries to stack active circuit layers vertically and connect them with very fine hybrid bonds, so circuits that need to talk are placed above and below each other instead of far apart on one plane.
The signal now takes a shorter route, the critical path becomes faster, clock timing becomes cleaner, and the same manufacturing node can deliver more performance.
Huawei is trying to win not by making every switch smaller, but by making every important signal travel less, wait less, and arrive sooner.