华为用 Tau Scaling 绕开光刻机限制，做芯片设计或关注半导体自主化的开发者值得了解——这可能改变未来芯片性能提升的路径。
华为在美国制裁压力下提出 Tau Scaling 定律，通过缩短信号传输延迟而非单纯缩小晶体管尺寸来提升芯片性能。其核心技术 LogicFolding 通过折叠逻辑块、缩短关键线路来降低电阻和寄生电容，实现更快的信号切换。华为声称已用此思路量产 381 款芯片，下一代麒麟手机芯片将首次全面验证 Tau Scaling。目标是在 2031 年达到 1.4nm 级密度，接近台积电和英特尔 2029 年的节点规划。这一突破可能改变芯片制造的游戏规则，绕开对先进光刻机的依赖。
🇨🇳 Huawei reveals a new chip design breakthrough …
🇨🇳 Huawei reveals a new chip design breakthrough under US sanctions pressure.
A design approach meant to close the gap with TSMC and Intel without relying only on smaller transistors, by making chip signals travel less distance.
They want 1.4nm-class density without owning the world’s best lithography tools i.e. they are trying to replace Moore’s Law with Tau Scaling Law.
To note, Huawei has been blocked from normal access to TSMC since the US tightened foreign direct product rules around Huawei in 2020, and TSMC later said it had not supplied Huawei since mid-September 2020.
Proposed τ Scaling as a new way to make chips faster when shrinking transistors is no longer delivering the same gains.
Said its next Kirin phone chip will be the first full test of Tau Scaling Law,
Old chip progress mostly came from making every transistor smaller, but Huawei’s idea shifts the target from smaller geometry to shorter signal delay, meaning less time wasted while electrical signals crawl through wires, gates, memory paths, and system links.
LogicFolding attacks the circuit layout itself by folding logic blocks closer together, shortening critical wires, reducing resistance and parasitic capacitance, and letting signals switch faster with denser placement.
So LogicFolding is the circuit-level piece: it tries to place related logic closer together, shorten key wires, cut electrical drag from resistance and parasitic capacitance, and raise performance without needing a full manufacturing-node leap.
Huawei is also pushing the same timing idea across the full stack: transistors, circuits, chip architecture, software scheduling, and system interconnects all get tuned to reduce τ, the delay constant that limits speed and efficiency.
The bold claim is that Huawei has already mass-produced 381 chips using this thinking, and future high-end chips could reach density comparable to 14Å, or 1.4nm, without relying only on classic process shrinkage.
Says this path could reach 1.4nm-class, or 14Å-class, density by 2031, while TSMC and Intel target similar physical nodes around 2029.
Huawei calls it Her’s Law, after He Tingbo, the chip leader who helped turn HiSilicon into Huawei’s survival engine after US export controls. ---
huawei. com/en/news/2026/5/ieee-iscas-tau-scaling