这论文把神经网路编译成纯布尔电路，在边缘设备上跑EEG分类，延迟低还省电。痴呆检测准确率比MLP高6.8%，值得搞BCI的人看看。
该研究提出Diff-Logic，将神经网络编译为纯布尔电路，通过位运算在CPU上执行。在四个EEG数据集（包括二分类痴呆检测和三分类情绪识别）上，与MLP和BNN基线对比，复杂度从50k到500k参数。痴呆检测中Diff-Logic达到80.2% Macro F1，比MLP高6.8%。在7W Nvidia Jetson Orin Nano单核CPU上，情绪识别任务中MLP性能略优但延迟是Diff-Logic的2.3倍，模型大小是14倍。Diff-Logic在模型规模扩大10倍时推理时间几乎不变，最大复杂度下速度提升达2.9倍。
Differentiable Logic Gate Networks for Low-Latency EEG Classification on Edge Devices
Real-time EEG classification on edge devices is bottlenecked by the floating-point arithmetic of conventional neural networks. We investigated Differentiable Logic Gate Networks (Diff-Logic) as a hardware-native alternative that compiles models into pure Boolean circuits executable via bitwise CPU operations. Through rigorous iso-parameter experiments across four EEG datasets spanning two classification tasks, binary dementia detection and 3-class emotion recognition, we compared Diff-Logic against matched-capacity Multi-Layer Perceptron (MLP) and Binarized Neural Network (BNN) baselines at four complexity tiers (50k-500k parameters). On dementia screening, Diff-Logic achieved 80.2% Macro F1, outperforming the MLP baseline by 6.8%. On emotion recognition, the MLP retained a moderate performance advantage but incurred a 2.3$\times$ higher latency and 14$\times$ larger model size when deployed on a power-constrained (7W) Nvidia Jetson Orin Nano CPU (Single-core). Critically, Diff-Logic inference time remained nearly constant across a 10$\times$ increase in model scale, achieving a peak speedup of 2.9$\times$ over MLPs at the largest complexity tier. Our results establish logic-based neural architectures as a practical paradigm for resource-constrained brain-computer interfaces, achieving competitive or superior performance while natively satisfying the latency and memory constraints of portable edge deployment. Code is available on GitHub: https://github.com/Shyamal-Dharia/eeg-difflogic