想看TPU五代真实进化数据和能效提升细节？这篇论文从256芯片到9216芯片、从风冷到水冷、30倍每瓦算力提升，全是硬货。
Jeff Dean宣布一篇将发表于IEEE Micro 2026年7/8月刊的论文，详细回顾Google从TPU v2到Ironwood共五代训练超算的架构演变。论文披露TPU每芯片每瓦TFLOPS提升了约30倍，每个pod的芯片数从TPU v2的256颗扩增至Ironwood的9216颗。冷却方式从风冷（TPU v2）转为水冷（TPU v3起），互连从2D torus升级为3D torus。论文还指出工作负载已大幅转向Transformer模型。
My @Google colleagues @NormJouppi, Sridhar Lakshmanamurthy, Cliff Young, and David Patterson recentl...
My @Google colleagues @NormJouppi , Sridhar Lakshmanamurthy, Cliff Young, and David Patterson recently wrote a paper that will appear in the July/August 2026 edition of @ieeemicro titled "Google's Training Supercomputers from TPU v2 to Ironwood: Architectural Stability, Scale, Resilience, Power Efficiency, and Sustainability Across Five Generations". It's chock full of interesting data about the evolution of TPU chip generations, as well as how workloads at Google have transformed over time (hint: lots more transformer-based models!), and how the generations have gotten ~30X more energy efficient per flop. Lots of changes over these generations: Air cooling in TPUv2 to water cooling in TPUv3 onwards 2D to 3D torus-based interconnects 30X improvement TFLOPS/Watt 256 chips (TPUv2) to 9216 chips (Ironwood) per pod Read the full paper: arxiv.org/abs/2606.15870 💬 7 🔄 32 ❤️ 155 👀 8234 📊 39 ⚡
- arXiv: OpenAI06-17 08:04原文