这篇论文研究了用忆阻器做储备池计算来加速CPU分支预测，Dhrystone测试表现不错，但比TAGE慢15倍，适合关注硬件AI加速的朋友看。
该论文提出了一种基于忆阻器的储备池计算（RC）设计框架，针对多级流水线CPU的分支预测（BP）任务。使用System Verilog和Verilog-AMS进行了仿真实现，在Dhrystone基准测试上评估，目标指令集为RISC-V RV64GC。实验显示RC能达到较高的整体预测准确率，但与最先进的TAGE预测器相比，适应分支行为变化的速度慢15倍。论文指出了进一步优化自适应能力的必要性。
Investigating reservoir computing for branch predictionin pipelined processors using emerging CMOS memristor devices
This project aimed to develop a novel reservoir compute (RC) implementation framework targeting high-speed operation and integration with CMOS digital logic. With the target workload of branch prediction (BP) for multistage pipelined central pro-cessing unit (CPU) cores. For this, a novel memristor based RC design framework was developed within the context of the workload requirements. This was then implemented in simulation using industry standard modelling languages of System Verilog (SV) and Verilog-AMS (VAMS).The developed RC design framework was subsequently verified using a basic sequence detection task before further benchmarking for its effectiveness at BP. The developed RC framework was tested using the Dhrystone performance benchmark, while targeting the RISC-V RV64GC instruction set architecture (ISA). Conducted testing demonstrates that RC shows great promise for ap-plication to BP and is capable of achieving impressive overall prediction accuracy. However, testing also shows that further refinement of the developed RC design framework is necessary to address shortfalls in the adaptability of the proposed RC system. As comparison against the state of the art TAGE predictor showed the proposed RC design framework to be 15x slower to adapt to changes in branching behaviour.