Micron 公布到 2030 年的 HBM4、3D DRAM 与 AI 级 NAND 路线图
Micron 这份 2030 存储路线图信息量很大：HBM4 带宽对标全球互联网、vertical HBM、3D DRAM 转向都在里面，做 AI 硬件的值得翻翻原文幻灯片。
Micron 在最新报告中披露了到 2030 年的存储芯片规划：单栈 HBM4 带宽达 2.8 TB/s，13 块顶级 AI GPU 各配 8 栈即可匹敌约 282 TB/s 的全球国际互联网带宽。Nvidia GPU 显存从 H100 的 80GB 增至 B300 的 288GB，Micron 估计 AI 上下文长度每年增长 30 倍。公司计划 2028 年推出 vertical HBM，把内存直接堆叠在 GPU 上方；内部用 AI 写芯片逻辑和固件后，SSD 控制器设计时间缩短 50%，交付准备缩短 60%。Micron 还放弃了研究 20 多年的 4F² DRAM 单元布局，转向 3D 堆叠 DRAM，与坚持 4F² 的 SK hynix 和 Samsung 分道扬镳。
Micron detailed the memory and storage chips it plans to bring to market through 2030 in its latest report.
Some revelations from the deck
> A single HBM4 memory stack moves 2.8 TB/s, so the memory inside roughly 13 top AI GPUs, at 8 stacks each, matches the world’s entire international internet capacity of about 282 TB/s. (Attach slide 12, “HBM4 vs. worldwide internet bandwidth”.)
> Memory per Nvidia GPU grew 3.6x from the H100’s 80GB to the B300’s 288GB, and Micron estimates AI context length is growing 30x a year. A robotaxi needs over 10x the memory of today’s driver-assist car. (Attach slide 5, “Each wave of AI increases memory demand”.)
> Micron plans “vertical HBM” by 2028, stacking memory directly on top of the GPU rather than beside it, which shortens the data path and yields more AI output per watt; Micron calls the dates targets. (Attach slide 20 for the simple picture, or slide 22 for the 2026 to 2030 roadmap.)
> AI agents that write and check chip logic, plus AI-written firmware, cut Micron’s time to finish an SSD controller design by 50% and to ready an SSD for customers by 60%, based on 2 internal programs. (Attach slide 27, “AI makes Micron 2x faster”.)
> After over 20 years studying a denser DRAM cell layout called 4F², Micron has abandoned it as too costly and complex, splitting from SK hynix and Samsung, which are pursuing it, and will build DRAM upward in 3D instead. (Attach slide 16, “DRAM roadmap”.)
> Micron is designing flash storage that GPUs can read directly in tiny chunks, plus HBM-style stacked flash beside the accelerator, to hold model weights and the working memory of long AI conversations, targeting 25M to 100M operations per second. (Attach slide 24, “AI-class NAND”.)
> Micron fits over 1,500 memory capacitors across the width of a single 50 µm human hair, and each DRAM wafer now holds over 400x more bits than in 1995, across 22 manufacturing generations. (Attach slide 9; slide 11’s Porsche comparison works as a companion.)
