双循环自动化框架：用自然语言生成可验证的电源电路原理图
From Natural Language to Real Schematics: An Automated Workflow for Power Electronics Schematic Synthesis
把需求描述直接变成能用 ngspice 跑通的 KiCad 电源原理图，仿真通过率从 0 拉到 100，做电源设计的可以看看这套流程。
arXiv 论文提出 Bounded Dual-Loop 框架，把自然语言规格转换为经过验证的 KiCad 原理图和制造交付物。工作流覆盖 Buck、Boost、Flyback、DAB、半桥 LLC 等拓扑，组件选型基于分销商 API 和 OEM 数据手册，并用 ngspice 瞬态仿真闭环验证。在 24-36V 转 12V/2A Buck 和 48V 转 24V/0.5A DAB 两个案例中，组件验证覆盖率从 22.2 提升到 98.6，标称值一致性从 0 提升到 97.7，SPICE 仿真通过率从 0 提升到 100。对比 Vanilla LLM 基线，该框架有效抑制了元件型号捏造和电压降额违规等工程幻觉。
From Natural Language to Real Schematics: An Automated Workflow for Power Electronics Schematic Synthesis
Designing power electronics converters traditionally requires intensive human expertise across topology sizing, commercial component selection, circuit simulation verification, and schematic drafting. While Large Language Models (LLMs) show promise in electronic design automation (EDA), applying standalone LLMs directly to board-level power electronics schematic synthesis suffers from severe engineering hallucinations, including inaccurate analytical sizing, fabricated or mismatched component part numbers, violated voltage derating margins, and broken topological connectivity. In this paper, we propose a Bounded Dual-Loop Automated Schematic Synthesis Framework that translates natural language specifications into verified, editable KiCad schematics and manufacturing deliverables. Our workflow integrates six stages across three functional columns: (1) requirement parsing and knowledge-driven power stage synthesis covering non-isolated (Buck, Boost) and isolated/resonant (Flyback, DAB, half-bridge LLC) topologies; (2) contract- and evidence-coordinated component selection grounded in distributor APIs and OEM datasheets, coupled with closed-loop ngspice transient verification and stress feedback; and (3) modular control hardware integration and multi-format deliverable generation featuring native KiCad netlist round-trip verification. End-to-end case studies on a 24-36V to 12V,2A Buck converter (29 positions, 83 verified terminals) and an isolated 48V to 24V, 0.5A, Dual-Active Bridge (DAB) converter (87 positions, 341 verified terminals), alongside comparative evaluations against a Vanilla LLM baseline, demonstrate that our framework improves component verification coverage from 22.2 to 98.6, nominal value consistency from 0 to 97.7, and SPICE simulation pass rates from 0 to 100.
