Siemens EDA lifts chip design agent score from 55% to 95%
The gains came from auditing agent outputs and rewriting tool descriptions, not from swapping in a bigger model — a cheaper lever most teams overlook. Engineering teams building agentic workflows can replicate the measure-and-refine loop described in NVIDIA's techblog. It pairs a concrete verification benchmark with a widely available framework, NeMo Gym, making the method transferable beyond chip design.
The Siemens EDA team used NVIDIA NeMo Gym to verify the engineering files its chip design agent produced, trace errors, and refine the agent's skills and tool descriptions. On the team's standard cell characterization benchmark, the composite verification score rose from about 55% to about 95%. The improvements also cut agent turns by 66% and output tokens by 64%. NVIDIA published a techblog detailing what was measured and changed.
How do you make a chip design agent more reliable and efficient? The @Siemens EDA team used NVIDIA NeMo Gym to check the engineering files its agent produced, trace errors, and improve the agent’s skills and tool descriptions. In its standard cell characterization benchmark, those changes raised the composite verification score from ~55% to ~95%, with 66% fewer agent turns and 64% fewer output tokens. We just published a new techblog that walks through what the team measured, what they changed, and how other engineering teams can apply the approach → nvda.ws/4Beujcb 💬 23 🔄 19 ❤️ 163 👀 13010 📊 49 ⚡
