AutoC2V：用综合反馈训练 LLM 生成更优 QoR 的 Verilog 代码
AutoC2V: Synthesis-Guided LLM Training for QoR-Optimized C++-to-Verilog Generation
做芯片设计或 HLS 的朋友可以看看这篇：AutoC2V 把真实综合结果变成训练数据，再用一个 QoR 预测奖励模型省掉反复跑综合的开销，生成的 RTL 在延迟和资源上比 HLSPilot、AutoDSE 和 Claude Opus 4.8、GPT-5.5 这些通用模型都好。
AutoC2V 是一个 C++ 转 Verilog 的 RTL 生成框架，核心是用真实综合（synthesis）反馈来训练大模型，让模型直接从可综合的 C++ kernel 生成延迟和资源占用更优的硬件设计。团队用真实综合结果构建训练数据，包含 C++ 源码、对应 Verilog RTL、QoR 指标和优化目标，再通过 SFT 和 GRPO 两个阶段做对齐。
为降低 GRPO 阶段反复调用真实综合工具的高成本，作者设计了 QoR Prediction Reward Model（QoR RM）：把 RTL 编码为长上下文语义表示，据此预测延迟和资源指标，从而以低成本提供连续的奖励信号供策略优化使用。
实验显示，AutoC2V 在 RTL 功能通过率上明显高于未微调的基座模型，延迟与资源优化也优于 HLSPilot、LLM-DSE、AutoDSE 等 HLS 优化方法，以及 Claude Opus 4.8、GPT-5.5、Gemini 3.1 Pro、DeepSeek v4 Pro、GLM-5.2 等通用商业模型。
AutoC2V: Synthesis-Guided LLM Training for QoR-Optimized C++-to-Verilog Generation
High-level synthesis (HLS) can translate C/C++ kernels into register-transfer level (RTL) designs, yet generating high-quality hardware still relies heavily on manual pragma tuning and repeated synthesis evaluation. We propose AutoC2V, a C++-to-Verilog generation framework driven by real synthesis feedback that enables large language models (LLMs) to directly generate RTL with improved quality of results (QoR) from synthesizable C++ kernels. We construct training data from real synthesis results, including synthesizable C++ source code, the corresponding Verilog RTL, QoR metrics, and optimization objectives. Using this dataset, we align the model toward synthesis-aware RTL generation through Supervised Fine-Tuning (SFT) and Group Relative Policy Optimization (GRPO). To reduce the high cost of repeatedly invoking real synthesis during GRPO, we design the QoR Prediction Reward Model (QoR RM), which predicts latency and resource metrics by encoding RTL into long-context semantic representations, thereby providing low-cost and continuous QoR reward signals for policy optimization. Experimental results demonstrate that AutoC2V not only substantially improves RTL functional pass rates, but also achieves superior latency and resource optimization compared to the unfine-tuned base model, representative HLS optimization approaches (HLSPilot, LLM-DSE, and AutoDSE), and advanced general-purpose commercial models (Claude Opus 4.8, GPT-5.5, Gemini 3.1 Pro, DeepSeek v4 Pro, and GLM-5.2). These results indicate that combining real synthesis data with efficient QoR reward modeling can further improve the ability of LLMs to generate high-quality RTL.
This report is categorized under AITOP's "Papers" desk. Within our cross-regional analytical framework, it directly maps to AI developer toolchains, coding agents, and engineering workflows. Key entities and technical topics under continuous tracking include AutoC2V, Verilog, HLS, GRPO.
Primary source verification: published directly by arXiv: DeepSeek with first-party authority.