Archgen 用 AI 设计 3D 芯片，热仿真速度快 5000 倍
YC F26 的 Archgen 在做 AI 驱动的 3D 芯片设计工具，热仿真比传统 EDA 快 5000 倍，布局引擎还拿了 HRT 挑战赛第一。芯片垂直堆叠后散热和时序是硬骨头，他们让 AI 智能体自己找 bug、修复、重跑。做芯片设计或关注 EDA 格局的人可以看看。
YC F26 批次的 Archgen 正在构建用 AI 设计三维芯片的工具，方向是把晶体管垂直堆叠以缩短连接距离。由于晶体管微缩越来越难，芯片走向立体化，但堆叠会带来散热与时序管理的难题。Archgen 的 AI 智能体可以读取每次设计运行的数据，定位失败原因，修复后自动重新运行，覆盖从单芯片到 3D 堆叠的设计流程。
技术上，Archgen 训练了用于热仿真的基础模型，温度预测速度比传统 EDA 工具快约 5000 倍；其布局引擎在 HRT 主办的 macro-placement 挑战赛中排名第一。团队还在与全球几家大型晶圆厂合作，计划 2027 年 4 月完成首颗芯片的 tape out。
把 EDA 中最耗时的热仿真和布局环节换成 AI 模型，如果 2027 年流片顺利，可能改变芯片公司设计 3D 堆叠芯片的成本结构，对被 Synopsys、Cadence 主导的 EDA 市场是一个新变量。
Chip design is next for AI. Transistors are getting harder to shrink, so chips are going vertical. Stacking them shortens connections but makes heat and timing much harder to manage. Archgen is building the tools to design chips in three dimensions. Their AI agent reads each design run, finds what's failing, fixes it, and reruns, from a single chip up to a 3D stack. hari_haran (building archgen YC F26) @HariAyapps @archgen_ is building skyscrapers for semiconductor chips Shrinking transistors is getting harder. Stacking them makes heat harder to manage. We’re building the tools to design chips in three dimensions. We stack transistors vertically, shorten connections, and optimize timing and heat together. Our foundational model for thermal simulation, predicts temperature roughly 5,000× faster than conventional EDA tools. Our placement engine ranked #1 in HRT’s macro-placement challenge We’re working with some of the largest fabs in the world to tape out our first chip in April 2027 archgenlabs.com
This report is categorized under AITOP's "Products" desk, focusing on US frontier AI labs and Silicon Valley technology leaders. Within our cross-regional analytical framework, it directly maps to AI developer toolchains, coding agents, and engineering workflows. Key entities and technical topics under continuous tracking include Archgen, EDA, 芯片设计, 3D堆叠.
Source attribution: curated from elvis (@omarsar0).
