VHDLBench：用 QLoRA 微调 7B 模型生成 VHDL 芯片设计代码
VHDLBench: Benchmarking and Fine-Tuning Large Language Models for VHDL-Based Chip Design
有人给 VHDL 代码生成做了个专门基准，18,500 多条样本微调后语法正确率到 92%，还真能跑上 FPGA 硬件，做芯片设计的可以看看。
论文发布 VHDLBench，包含 18,500+ 条经过语法校验的 VHDL 样本，来源为开源仓库和 Verilog 转换。团队用 QLoRA 微调了五个 7B 参数模型，评测采用语法综合、testbench 功能仿真、Zynq SoC FPGA 原型验证三级流水线。结果显示微调后模型语法正确率最高达 92%，常见设计任务功能准确率 73%，其中 DeepSeek-Coder 提升最大。生成的设计已部署到真实硬件上运行。
VHDLBench: Benchmarking and Fine-Tuning Large Language Models for VHDL-Based Chip Design
The rapid evolution of digital circuit complexity demands innovative approaches to hardware design automation. While Large Language Models (LLMs) have influenced software development, their application to Hardware Description Language (HDL) generation remains largely unexplored, particularly for VHDL. This paper presents a comprehensive study for AI-assisted digital circuit design, addressing gaps in current Electronic Design Automation workflows. The work introduces a VHDL dataset of 18,500+ syntax-verified examples from open-source repositories and converted Verilog designs. Five 7B-parameter LLMs were fine-tuned using parameter-efficient QLoRA technique, enabling deployment in resource-constrained environments. To evaluate model efficacy, a rigorous three-level pipeline was established: (1) syntax and synthesis validation, (2) functional simulation with testbenches, and (3) FPGA prototyping on Zynq SoCs. Results show fine-tuned models achieve up to 92% syntax correctness and 73% functional accuracy on common design tasks, with DeepSeek-Coder demonstrating the highest performance gains. Generated designs were successfully deployed on real hardware, confirming not only syntactic but operational viability. This work demonstrates that LLMs, when tailored with domain-specific data and lightweight fine-tuning can contribute meaningfully to the future of generative EDA workflows.
