这篇论文把 chiplet 和 LLM 两个热点合在一起聊硬件安全，既有攻击面分析也有防御方案，做芯片安全的值得看看。
这篇论文统一分析了 chiplet 与 LLM 时代硬件攻击面的扩展，覆盖架构、逻辑和物理三个层面。针对 2.5D chiplet 系统，论文提出利用 2.5D split manufacturing 和 active interposers 构建物理隔离的 Root of Trust 防御架构。针对 LLM 驱动的 EDA 流水线，论文识别了原生威胁并梳理了现有防御技术。论文还探讨了 LLM 系统如何用于增强 chiplet 等现代系统的硬件安全。
Hardware Design and Security in the Era of Chiplets and LLMs
The semiconductor industry is undergoing a dual revolution: the shift toward heterogeneous 2.5D chiplet systems and the integration of Large Language Models (LLMs) into Electronic Design Automation (EDA) flows. While these paradigms offer unprecedented benefits in yield, modularity, design productivity, etc., they radically expand the hardware attack surface. This paper provides a unified analysis of these frontiers, ranging from attacks on chiplet systems (including hardware stacks for LLM acceleration) across architectural, logical, and physical levels, to various exploits against LLM-driven EDA pipelines. To secure chiplet systems, we review a powerful defense approach that leverages 2.5D split manufacturing and active interposers for physically isolated Root of Trust (RoT) architectures. To secure LLM-driven EDA pipelines, we first identify native threats and then review state-of-the-art defense techniques. Finally, we discuss how LLM systems can advance hardware security efforts for modern systems, including chiplets.