YC 创业公司 Archgen 用 3D 堆叠晶体管设计芯片，宣称降低 40% 功耗
这家叫 Archgen 的 YC 公司把晶体管往楼上盖，而不是继续往小里做，同一份活最多省 40% 电。他们的 AI 温度预测模型比传统软件快 5000 倍，工程师画芯片时就能当场看到哪里会过热。做芯片设计或关注后摩尔时代路线的人可以看看。
YC 孵化的创业公司 Archgen 正在改变芯片设计思路：传统芯片依靠缩小晶体管来提升性能，但这条路线已越来越难。Archgen 转而将晶体管像摩天大楼一样垂直分层堆叠，让信号传输距离更短。
堆叠层会带来散热难题，为此 Archgen 训练了一个 AI 模型来预测芯片温度，速度比标准芯片设计软件快约 5000 倍，工程师在设计阶段就能发现热点区域。同时，更短的导线电容更低，每次开关消耗的能量更少、信号稳定更快，Archgen 给出的数据是完成相同工作最多可省 40% 功耗。
在摩尔定律接近物理极限的背景下，3D 堆叠加上 AI 辅助热仿真，为芯片性能提升提供了另一条路径，对追求低功耗的芯片设计团队有直接参考价值。
Chips have mostly improved by shrinking transistors, and that is getting very hard.
so YC startup @archgen_ is designing chips that stack transistors in layers like a skyscraper, letting signals travel shorter distances and use less power.
Stacking chip layers is possible, but the stack traps heat, so Archgen built an AI model that predicts chip temperature about 5,000x faster than standard chip design software. i.e. it will let engineers find hot spots while they design.
And shorter wires carry less capacitance, so every switch costs less energy and settles faster. Archgen’s figure is up to 40% less power for the same work.
This report is categorized under AITOP's "Products" desk, focusing on US frontier AI labs and Silicon Valley technology leaders. Within our cross-regional analytical framework, it directly maps to AI developer toolchains, coding agents, and engineering workflows. Key entities and technical topics under continuous tracking include Archgen, 芯片设计, 3D堆叠, 功耗优化.
Source attribution: curated from rohanpaul_ai (@rohanpaul_ai).
