Constructive proof sets matrix multiplication exponent at 9/4

Smarter scheduling, not a smaller model, is what makes a 35B-parameter MoE fit and run fast on consumer phones — no retraining required, since routing stays untouched. Developers building on-device multimodal apps can grab the code and weights from GitHub and Hugging Face to run large models where cloud calls are impractical. It also shows open-source Chinese labs pulling ahead on mobile inference efficiency, a space Apple and Qualcomm stack owners care about.

OpenBMB@OpenBMBSource

PyTorch developers can now target TPU hardware through the same APIs they already use, reducing the migration cost that historically kept most teams on NVIDIA GPUs. Teams running training or inference pipelines with TorchTitan, vLLM, or SGLang can evaluate TPUs without rewriting code. The use of agents for kernel generation and sharding also hints at how optimization work itself may be automated.

官方账号PyTorch@PyTorchSource

The shift from point-in-time scanning to findings that auto-resolve and reopen as code evolves means security teams spend less time triaging stale reports. AppSec engineers and platform teams on Claude Enterprise can trial it with the bundled credits before the 31 December 2026 window ends, making it a direct alternative to point-in-time scanners like Snyk or GitHub code scanning.

rohanpaul_ai@rohanpaul_aiSource

The cost crossover at 6.8K tokens/s/chip reframes the Ascend-versus-Blackwell debate from raw benchmark losses to workload-dependent economics, suggesting DeepSeek could run its API on a sub-US$1B Blackwell cluster while pivoting post-training to Ascend. Practitioners tracking inference infrastructure or Huawei's CANN ecosystem get a rare concrete per-chip price and throughput comparison. The proposed 128-chip Ascend supernode topology has no Nvidia equivalent, which matters for anyone planning large-scale decode deployments.

Teortaxes@teortaxesTexSource

The bonding method determines the outcome: 3DS adds capacity at DRAM speeds, while hybrid bonding delivers bandwidth much closer to SRAM, deciding how few chips are needed to serve large models fast. Inference infrastructure teams evaluating Groq-class LPUs versus Nvidia GPUs, and anyone tracking Cerebras, which plans DRAM stacking on its CS-6 wafer, should watch which route ships first. Capacity, not bandwidth, is emerging as the binding constraint across SRAM-first architectures.

rohanpaul_ai@rohanpaul_aiSource

The notable point is that one config setup now covers three different training backends on Trainium, so teams can switch between them without rewriting launch scripts or breaking checkpoint compatibility. Engineers choosing between NVIDIA GPUs and AWS silicon can use this to evaluate Trainium for fine-tuning open-source models like Qwen3. The guide also shows how NKI MoE kernels fit into the same workflow.

官方一手AWS Machine Learning Blog@Josh LongeneckerSource

AI coding assistants raise the volume of changes per release, which multiplies the ways a large codebase can break — making crash prevention practices more urgent, not less. Mobile engineers and platform leads can compare their own rollout, monitoring and triage setups against Grab's layered pipeline. The write-up is a rare detailed look at superapp stability engineering from a Southeast Asian company operating at Google Play scale.

The speed of an optimizer depends as much on kernel-level linear algebra as on step count, a factor most training guides ignore. Engineers tuning large-scale training can apply the QR, Cholesky and eigendecomposition implementation patterns to cut data movement on GPUs. The talk ties directly to GPU MODE's competition, giving concrete reference implementations to study.

官方账号PyTorch@PyTorchSource